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july 2007 rev 1 1/33 AN2549 application note porting an application from th e st10f269zx to the st10f272z2 introduction the st10f272z2 is a new member of the stmicroelectronics st10 family of 16-bit single- chip cmos microcontrollers. it is functio nally upward compatible with the st10f269zx. the goal of this document is to highli ght the differences between st10f269zx and st10f272z2 devices. it is intended for hardware or software designers who are adapting an existing application based on the st10f269zx to the st10f272z2. this document presents the st10f272z2?s modified functionalities and the new ones, and goes on to describe the modified and the new registers. for each part, the differences with the st10f269zx that may have an impact when replacing the st10f269zx by the st10f272z2 are stressed and some advice is given on the way they can be handled. www.st.com
AN2549 contents 2/33 contents 1 modified features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 xram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 flash eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4 a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.5 real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.6 can modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.7 port input control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.8 ports output control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.9 pll and main on-chip oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 new features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1 additional xperipherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2 programmable divider on clkout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3 new multiplexer for x-interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4 additional ports input control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3 modified registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 xpercon register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4 new registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 xadrs3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2 xperemu register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.3 emulation-dedicated registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.4 xmisc register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2 ac characteristics at 40 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
AN2549 modified features 3/33 1 modified features 1.1 pinout 1.1.1 pinout modification summary ta bl e 1 summarizes the modifications made to the pinout. 1.1.2 pin 17 on the st10f269zx, a decoupling capacitor of 330nf minimum has to be connected between the pin 17 (named dc2) and the nearest v ss pin. this is no longer the case for the st10f272z2 device where pin 17 is a v dd pin. hardware impact pcb must be adapted. software impact none. table 1. pinout modifications pin number st10f269zx st10f272z2 name function name function 17 dc2 internal voltage regulator decoupling. connect to nearest v ss via a 330nf capacitor. v dd 5v power supply pin 56 dc1 internal voltage regulator decoupling. connect to nearest v ss via a 330nf capacitor. v 18 internal voltage regulator decoupling. connect to nearest v ss via a 10 - 100nf capacitor. 99 ea selects code execution out of internal flash memory or external memory according to level during reset. ea -v stby selects code execution out of internal flash memory or external memory according to level during reset. power supply input for the standby mode. 143 v ss ground pin xtal3 input to the 32 khz oscillator amplifier circuit. when not used, must be tied to ground to avoid consumption. additionally, bit off32 in rtccon register must be set. 144 v dd 5v power supply pin xtal4 output of the 32 khz oscillator amplifier circuit. when not used, must be left open to avoid spurious consumption.
AN2549 modified features 4/33 1.1.3 pin 56 on the st10f269zx, a decoupling capacitor of 330nf minimum has to be connected between the pin 56 (named dc1) and the nearest v ss pin. on the st10f272z2, pin 56 is named v 18 and a capacitor of value between 10nf minimum and 100nf maximum must be connected between it and the nearest v ss pin. hardware impact change on the capacitor value. as the value is much lower, the footprint of the capacitor might be smaller and then a modification of the pcb is needed. software impact none. 1.1.4 pin 99 on the st10f269zx, pin 99 is ea and used upon reset to select the start from the internal flash memory or the external memory. on the st10f272z2, pin 99 has the additional function of providing the 5v power supply to the device in standby mode (new power-saving mode), it is called ea -v stby . hardware impact the modification depends on the previous use of the st10f269zx and on whether the standby mode is used or not. for an application where the standby mode is not used, no change to the pcb is required. if the new application uses the standby mode, the ea -v stby pin must be separated from the common 5v and have a specific supply path. software impact none. 1.1.5 pins 143 and 144 these pins are v ss and v dd , respectively, in the st10f269zx. on the st10f272z2 they are used as xtal3 and xtal4 for connection to an optional 32 khz crystal to clock the real time clock during power-down. hardware impact pcb must be redesigned. if the optional 32 khz is not used: pin 143 (xtal3) must be linked to ground like on the st10f269zx pin 144 (xtal4) must be left open. it can also be connected to ground via a capacitor to reduce the potential rf noise that might be propagated inside the device if the pin is left floating.
AN2549 modified features 5/33 software impact in case the optional 32 khz is not used, the off32 bit of the rtccon register must be set. prior to setting the off32 bit in the rtccon register, the rtc must be enabled by setting rtcen, bit 4 of xpercon, and xpen, bit 2 of syscon. 1.2 xram the st10f269zx has 10 kbytes of extension ram whereas the st10f272z2 has 18 kbytes. the xram of the st10f269zx is divided into two ranges being xram1 of 2 kbytes and xram2 of 8 kbytes: the xram1 address range is 00?e000h - 00?e7ffh if enabled. the xram2 address range is 00?c000h - 00?dfffh if enabled. the xram of the st10f272z2 is divided into two ranges being xram1 of 2 kbytes (compatible with the st10f269zx) and xram2 of 16 kbytes with a user reprogrammable address range: the xram1 address range is 00?e000h - 00?e7 ffh if enabled (xpen and xram1en, bit 2 of syscon register and bit 2 of xpercon register, respectively, must be set). the xram2 address range is 09?0000h - 09?3fffh, by default (mirrored every 16 kbytes in the range 09?00 00h -0f?ffffh), if ena bled (xpen and xram2en, bit 2 of syscon register and bit 3 of xpercon re gister, respectively, must be set). hardware impact none. software impact there is no change in the enabling of the xram blocks: xpercon register bits, xram1en and xram2en, and syscon register bit, xpen, are used to enable them. the memory mapping of the application is impacted by the difference in xram size and by the location of xram2. a new register has been created in order to allow the user to remap the xram2 (please refer to section 4.1: xadrs3 register on page 23 for details). 1.3 flash eeprom table 2. flash memory key characteristics characteristic st1 0f269zx st10f272z2 flash size 256 kbytes 256 kbytes flash organization 7 blocks 8 blocks programming voltage 5 volts 5 volts programming method write/erase controller write/erase controller program / erase cycles 100000 cycles 100000 cycles
AN2549 modified features 6/33 1.3.1 hardware impact none. 1.3.2 software impact as the first 32 kbytes of flash memory are now divided into four sectors of 8 kbytes each in the st10f272z2 whereas the st10f269zx had only three sectors, the mapping of the application is impacted. moreover, the flash memory write/erase controller is different and therefore the programming routines must be updated. when the bit romen of the syscon register is set, that is, when the internal flash memory is enabled, accesses to the address range 05?0000h - 07?ffffh are not redirected to external memory. the linker-locator configuration of the toolchain should be checked in order to prevent any use of this memory range. table 3. flash memory mapping segment st10f269zx flash mapp ing st10f272 flash mapping 8 08?0000-08?ffff external memory 08?0000-08?ffff flash registers 7..5 05?0000-07?ffff external memory 05?0000-07?ffff reserved 4 04?0000-04?ffff block6: 64 kbytes 04?0000-04?ffff block7: 64 kbytes 3 03?0000-03?ffff block5: 64 kbytes 03?0000-03?ffff block6: 64 kbytes 2 02?0000-02?ffff block4: 64 kbytes 02?0000-02?ffff block5: 64 kbytes 1 01?8000-01?ffff block3: 32 kbytes 01?8000-01?ffff block4: 32 kbytes 01?0000-01?7fff external memory or remap of blocks 0-2 01?0000-01?7fff external memory or remap of blocks 0-3 0 00?8000 - 00?ffff external memory internal ram and registers 00?8000 - 00?ffff external memory internal ram and registers 00?6000 - 00?7fff block 2: 8 kbytes 00?6000 - 00?7fff block3: 8 kbytes 00?4000 - 00?5fff block 1: 8 kbytes 00?4000 - 00?5fff block2: 8 kbytes 00?0000 - 00?3fff block 0: 16 kbytes 00?2000 - 00?3fff block1: 8 kbytes 00?0000 - 00?1fff block0: 8 kbytes
AN2549 modified features 7/33 1.4 a/d converter in the st10f272z2, the analog/digital converter has been redesigned (compared to the a/d converter in the st10f269zx). the st10f272z2 still provides an analog/digital converter with 10-bit resolution and an on-chip sample and hold circuit. 1.4.1 hardware / software impact: conversion timing control the a/d converter in the st10f272z2 is not fully compatible with that of the st10f269zx (timing and programming model). in the st10f269zx, the sample time (to charge the capacitors) and the conversion time are programmable and can be adjusted to the external circuitry. the total conversion time is compatible with the formula used for st10f269zx, whereas the meanings of the adctc and adstc bit fields are no longer compatible. the user should take care of the sample time parameter: this is the time during which the capacitances of the converter are charge d via the respective analog input pins. ta bl e 5 shows the difference s in sample time. table 4. st10f272z2 conversion timing table adctc adstc sample comparison extra total conversion 00 00 tcl * 120 tcl * 240 tcl * 28 tcl * 388 00 01 tcl * 140 tcl * 280 tcl * 16 tcl * 436 00 10 tcl * 200 tcl * 280 tcl * 52 tcl * 532 00 11 tcl * 400 tcl * 280 tcl * 44 tcl * 724 11 00 tcl * 240 tcl * 120 tcl * 52 tcl * 772 11 01 tcl * 280 tcl * 560 tcl * 28 tcl * 868 11 10 tcl * 400 tcl * 560 tcl * 100 tcl * 1060 11 11 tcl * 800 tcl * 560 tcl * 52 tcl * 1444 10 00 tcl * 480 tcl * 960 tcl * 100 tcl * 1540 10 01 tcl * 560 tcl * 1120 tcl * 52 tcl * 1732 10 10 tcl * 800 tcl * 1120 tcl * 196 tcl * 2116 10 11 tcl * 1600 tcl * 1120 tcl * 164 tcl * 2884
AN2549 modified features 8/33 in the default configuration the sample time of the st10f272z2 is 2.5 times longer compared to that of the st10f269zx. this has an impact on the frequency of the input signal that can be applied to the st10f272z2. 1.4.2 hardware impact: el ectrical characteristics ta bl e 6 lists the differences in the dc characteristics of the two devices. table 5. st10f272z2 vs st10f269zx sample time comparison table adctc adstc st10f269zx sample time st10f272z2 sample time ratio f272z2_time / f269_time 00 00 tcl * 48 tcl * 120 2.5 00 01 tcl * 96 tcl * 140 1.46 00 10 tcl * 192 tcl * 200 1.04 00 11 tcl * 384 tcl * 400 1.04 11 00 tcl * 96 tcl * 240 2.5 11 01 tcl * 192 tcl * 280 1.46 11 10 tcl * 384 tcl * 400 1.04 11 11 tcl * 768 tcl * 800 1.04 10 00 tcl * 192 tcl * 480 2.08 10 01 tcl * 384 tcl * 560 1.46 10 10 tcl * 768 tcl * 800 1.04 10 11 tcl * 1536 tcl * 1600 1.04 table 6. adc differences symbol parameter limit values for st10f269zx l imit values for st10f272z2 unit min max min max v aref analog reference voltage 4.0 v dd + 0.1 4.5 v dd v v ain analog input voltage v agnd v aref v agnd v aref v c ain adc input capacitance (port 5) not sampling sampling - - 10 15 - - c p1 + c p2 +c s 7 10.5 pf t s sample time 48tcl 1536tcl 1s 120tcl 1600tcl t c conversion time 388tcl 2884tcl 388tcl 2884tcl tue total unadjusted error (port5) -2.0 +2.0 -2.0 +2.0 lsb r asrc internal resistance of analog source t s [ns]/150-0.25 k ?
AN2549 modified features 9/33 note: the v aref pin is also used as a supply pin for t he adc module. as there is a higher current sink on this pin on the st10f272z2 compared to the st10f269zx, it is recommended not to connect a resistor (for example, because of an rc filter), to prevent creating an offset in the reference. 1.4.3 software impact self-calibration and adc initialization routine an automatic self-calibration adjusts the adc module to process parameter variations at each reset event. after reset, the busy flag (read-only) adbsy is set because the self- calibration is ongoing. the duration of self-calibration depends on the cpu clock: it may take up to 40.629 1 clock pulses. the user must poll this bit to know when self-calibration is complete in order to initialize the adc module. this self-calibration is seen by the st10f272z 2 as a conversion and thus bit adcir is set. the software should perform a dummy read of the addat register and clear the adcir and adceir flags before configuring the adc module and starting the first conversion. new bit adoff, bit 6 of adcon register the bit 6 of the adcon register, reserved in previous st10 devices, is now used to enable and disable the adc. by default this bit is cleared and the st10f272z2 is compatible with the st10f269zx. therefore, there is no impact on the software, provided that this bit is not written to. i aref reference supply current running mode power-down mode - - 500 1 - - 5000 1 a a dnl differential nonlinearity -0.5 +0.5 -1 +1 lsb inl integral nonlinearity -1.5 +1.5 -1.5 +1.5 lsb ofs offset error -1.0 +1.0 -1.5 +1.5 lsb table 6. adc differences (continued) symbol parameter limit values for st10f269zx l imit values for st10f272z2 unit min max min max adcon (ffa0h / a0h) sfr reset value: 0000h 15 14 13 12 11 10 9 8 76543210 adctc adstc ad crq ad cin ad wr ad bsy ad st ad off adm adch r/w r/w r/w r/w r/w ro r/w r/w r/w r/w table 7. adcon register description bit function comment adoff adc disable 0: analog circuitry of a/d converter is on 1: analog circuitry of a/d converter is turned off new bit valid only for the st10f272z2. reserved on st10f269zx.
AN2549 modified features 10/33 additional channels on port1 a new multiplexer selects one out of up to 16 + 8 analog input channels (alternate functions of port 5 and port1). the selection of port1 or port5 as the input of the adc is made via bit adcmux, bit 0 of the xmisc register. by default the multiplexer selects port5, so there is no impact on the software as compared to an st10f269zx implementation. note that xmiscen, bit 10 of the xpercon register, must be set to have access to the xmisc register. 1.5 real time clock the rtc module can be clocked by two differ ent sources: the main oscillator (pins xtal1 and xtal2) or the 32 khz oscillator (pins xtal 3 and xtal4). the selection of the clocking can be made via an additional bit in the rtccon register. 1.5.1 hardware impact check the usage of pins xtal3 and xtal4 (pins 143 and 144, respectively). 1.5.2 software impact the address range of the rtc registers has been modified from 00?ec00h - 00?ecffh on the st10f269zx, to 00?ed00h - 00?edffh on the st10f272z2. this relocation has no impact if the software uses register names defined by the toolchain and if the cpu selection is changed to st10f272z2. if the software was directly using the address of the rtc register, it must be modified according to the new mapping. xmisc (eb46h) xreg reset value: --00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved vreg off can ck2 can pa r adc mux - r/w r/w r/w r/w table 8. xmisc register description bit function adcmux adc multiplexer 0: default configuration, analog inputs on port p5.y can be converted 1: analog inputs on port p1.z can be converted, only 8 channels can be managed st10f269zx: rtccon (f1c4h / e2h) esfr reset value: --00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved rtc off reserved rtc aen rtc air rtc sen rtc sir - r/w - r/w r/w r/w r/w st10f272z2: rtccon (f1c4h / e2h) esfr reset value: 0000h 15 14 13 12 11 10 9 8 7654 3 2 1 0
AN2549 modified features 11/33 the handling of the rtcair and rtcsir flags (bits 2 and 0 of the rtccon register, respectively) has also changed: in the st10f272z2, these flags are cleared by writing them to ?1? in the st10f269zx, these flags are cleared by writing them to ?0? as these flags must be cleared by software when entering the corresponding interrupt service routine, a change in the application code is needed. example for rtcsir flag replace st10f269zx code: rtccon &= 0xfffe;// clear rtcsir flag reserved off 32 osc rtc off reserved rtc aen rtc air rtc sen rtc sir -r/w ro r/w - r/w r/w r/w r/w table 9. rtccon register description bit function reset value rtcsir rtc second interrupt request flag (every basic clock unit) 0: the bit was reset less than a basic clock unit ago. 1: the interrupt was triggered. 0 rtcsen rtc second interrupt enable 0: rtc_secit is disabled. 1: rtc_secit is enabled; it is generated every basic clock unit. 0 rtcair rtc alarm interrupt request flag (when the alarm is triggered) 0: the bit was reset less than n basic clock units ago. 1: the interrupt was triggered. 0 rtcaen rtc alarm interrupt enable 0: rtc_alarmit is disabled. 1: rtc_alarmit is enabled. 0 rtcoff rtc switch off bit 0: clock oscillator and rtc keep on running even if st10 is in power down mode. 1: clock oscillator is switched off when st10 enters power down mode. additionally, when setting this bit, rtc dividers and counters are stopped and registers can be written. 0 osc oscillator selection flag 0: the clock oscillator used by the rtc is the main oscillator. 1: the clock oscillator used by the rtc is the low power 32 khz oscillator. 0 off32 32 khz oscillator switch off bit 0: the 32 khz oscillator is enabled. the rtc is clocked with 32 khz if there is a valid signal. 1: the 32 khz oscillator is disabled. the rtc is clocked by the main oscillator. 0
AN2549 modified features 12/33 by the following code for st10f272z2: rtccon |= 0x0001;// write 1 into rtcsir flag to clear it 1.6 can modules the st10f269zx has two can modules of the b-can type. the st10f272z2 has two can modules of the c-can type. these modules are functionally compatible with the modules of the st10f269zx. the c-can cells provide additional message ob jects and new function alities. the main difference is that the message objects are no longer directly accessed as memory but are available through a message interface. this changes the programming model of the modules. 1.6.1 hardware impact none. 1.6.2 software impact rewrite the can drivers. 1.7 port input control in the st10f269zx, the port input control register picon is used to select between ttl and cmos-like input thresholds. the cmos-like input thresholds are defined above the ttl levels and feature a hysteresis of 250mv to prevent the inputs from toggling while the respective input signal level is near the thresholds. this feature is available for all pins of port 2, port 3, port4, port 7 and port 8. in the st10f272z2, port 6 has been added. moreover, the default hysteresis is now 500mv for ttl levels and 800mv for cmos levels. st10f269zx: picon (f1c4h / e2h) esfr reset value: --00h 1514131211109876543210 reserved p8 lin p7 lin res. p4 lin p3 hin p3 lin p2 hin p2 lin - r/w r/w - r/w r/w r/w r/w r/w st10f272z2: picon (f1c4h / e2h) esfr reset value: 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved p8 lin p7 lin p6 lin p4 lin p3 hin p3 lin p2 hin p2 lin - r/w r/w r/w r/w r/w r/w r/w r/w
AN2549 modified features 13/33 1.7.1 hardware impact none. 1.7.2 software impact none if the software is not wr iting to picon bit 5 (p6lin). 1.8 ports output control in the st10f269zx, the port output control registers poconx are used to select the output driver characteristics of a port. in this way, the output drivers can be adapted to the application?s requirements, and eventually, the emi behavior of the device can be improved. two characteristics may be selected: edge characteristic defines the rise/fall time for the respective outputs, that is, the transition time. slow edge reduces the peak currents that are sunk/sourced when changing the voltage level of an external capacitive load. driver characteristic defines either the general driv ing capability of the respective drivers, or if the driver strength is reduced after the target output level has been reached or not. reducing the driver strength increases the output?s internal resistance, which attenuates noise that is imported via the output line. this feature is not available on the st10f272z2. 1.8.1 hardware impact some modifications might be needed depending on the usage of this functionality. 1.8.2 software impact parts related to the initia lization of the poconx registers should be suppressed. 1.9 pll and main on-chip oscillator compared to the st10f269zx, several modifications have been introduced: pll multiplication factors have been adapted in order to match the new frequency range. on-chip main oscillator input frequency range has been resha ped, reducing it to 4 to 8 mhz: this allows the power consumption to be reduced when the real time clock is table 10. picon register description bit function reset value pxlin port x low byte input level selection 0: pins px.7..0 switch on standard ttl input levels 1: pins px.7..0 switch on cmos input levels 0 pxhin port x high byte input level selection 0: pins px.15..8 switch on standard ttl input levels 1: pins px.15..8 switch on cmos input levels 0
AN2549 modified features 14/33 running in power down mode and the on-chi p main oscillator clock is used as the reference. when the pll is used, the cpu frequency range is 16 to 64 mhz. figure 1: st10f272z2 clock generation diagram gives a simplified description of the cpu clock generation. depending on the multiplication factor selected via port0 at reset, values are set for each stage. the cpu clock is in fact generated mainly from a vco with the following characteristics: input range: 1 to 3.5 mhz, which explains the prescaler that divides the xtal frequency output range: 64 to 128 mhz that is then divided through divider1 to generate the cpu clock figure 1. st10f272z2 clock generation diagram table 11: st10f269zx vs st10f272z2 pll ratio lists the new pll multiplication factors and the corresponding frequency ranges for the st10f272z2. table 11. st10f269zx vs st10f272z2 pll ratio p0.15-13 (p0h.7-5) pll multiplication factor st10f272z2 main oscillator st10f269zx st10f272z2 input range (mhz) cpu clock range (mhz) 1 1 1 x 4 x 4 4 to 8 16 to 32 1 1 0 x 3 x 3 5.34 to 8 16.02 to 24 1 0 1 x 2 x 8 4 to 8 32 to 64 1 0 0 x 5 x 5 6.4 to 8 32 to 40 0 1 1 x 1 x 1 1 to 64 1 to 64 0 1 0 x 1.5 x 10 4 to 6.4 40 to 64 0 0 1 x 0.5 x 0.5 4 to 8 2 to 4 0 0 0 x 2.5 x 16 4 64 prescaler vco divider1 f cpu divider2 phase comparator f xtal
AN2549 modified features 15/33 1.9.1 hardware impact port0 configuration might be changed with regards to the new pll factor. all configurations need a crystal (or ceramic resonator) to generate the cpu clock through the internal oscillator amplifier, except for the direct drive mode (oscillator amplifier disabled, so no crystal or resonator can be used). vice versa, the clock can be forced through an external clock source only in direct drive mode. the components on xtal1 and xtal2 (crystal and capacitors, or resonator) must be changed as: the input frequency range is now reduced it is no longer possible to use a crystal or a ceramic resonator in direct drive mode it is no longer possible to use a pll factor with a frequency generator the electrical characteristics of the main oscillator have changed (transconductance) 1.9.2 software impact none.
AN2549 new features 16/33 2 new features 2.1 additional xperipherals some peripherals have been added to the st10f272z2. they are mapped on the xbus and are linked to additional alternate functions of some ports of the st10f272z2. the additional xperipherals are the following: a second ssc (ssc of st10f269zx becomes ssc0, while the new one is referred to as xssc or simply ssc1). note that some restrictions and functional differences due to the xbus peculiarities ar e present between the standa rd ssc, and the new xssc. a second asc (asc0 of st10f269zx remains asc0, while the new one is referred to as xasc or simply as asc1). note that so me restrictions and functional differences due to the xbus peculiarities are present between the standard asc, and the new xasc. an i2c interface is added (see x-i2c or simply i2c interface). in addition to the previous xperipherals, the st10f272z2 also features a second pwm (pwm of st10f269zx becomes pwm0, while the new one is referred to as xpwm or simply as pwm1). note that some restrictions and functional differences due to the xbus peculiarities are present between the standard pwm, and the new xpwm. 2.1.1 hardware impact none if the additional xperipherals are not used. 2.1.2 software impact none if the additional peripherals are not used. as they are xperipherals, they can be enabled / disabled via the xpercon and syscon registers. by defa ult, the settings of xpercon and syscon are compat ible with the st10f269zx. 2.2 programmable divider on clkout a specific register mapped on the xbus is used to choose the division factor on the clkout signal (p3.15). xclkoutdiv (e902h) xbus reset value: --00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved div -r/w table 12. xclkoutdiv register description bit function div f clkout = f cpu / (div + 1)
AN2549 new features 17/33 2.2.1 hardware impact none. 2.2.2 software impact none if only clkout is needed. when the clkout function is enabled by setting the clken bit in the syscon register, by default the cpu clock is output on p3.15. to have access to the xclkoutdiv register, and thus to program the clock pre-scaling factor, the xmiscen bit in the xpercon r egister and the xpen bit in the syscon register must be set. 2.3 new multiplexer for x-interrupts the limited number of xbus interrupt lines of the present st10 architecture imposes some constraints on the implementation of the new functionalities. in particular, the additional xperipherals xssc, xasc, xi2c and xpwm need some resources to implement interrupt and pec transfer. for this reason, a complex but very flexible multiplexed structure for the interrupt is proposed. in figure 2 , the principle is represented through a simple diagram, which shows the basic structure replicated for ea ch of the four x-interrupt vectors (xp0int, xp1int, xp2int and xp3int). it is based on a new 16-bit register xirxsel (x = 0,1,2,3), divided into 2 bytes: higher byte (xirxsel[15:8]) interrupt enable bits lower byte (xirxsel[7:0]) interrupt flag bits figure 2. x-interrupt basic structure when different sources submit an interrupt request, the enable bits (byte high of xirxsel register) define a mask which controls which sources will be associated with the unique available vector. if more than one source is enabled to issue the request, the service routine has to identify the real event to be serviced. this can easily be done by checking the flag xir x sel[7:0] (x = 0, 1, 2, 3) xir x sel[15:8] (x = 0, 1, 2, 3) xp x ic . ir (x = 0, 1, 2, 3) 70 15 8 it source 7 it source 6 it source 5 it source 4 it source 3 it source 2 it source 1 it source 0 enable[7:0] flag[7:0]
AN2549 new features 18/33 bits (byte low of xirxsel register). note that the flag bit can provide information about events which are not currently serviced by the interrupt controller (since masked through the enable bits), allowing an effective software management also in the absence of the possibility to serve the related in terrupt request: a pe riodic polling of the flag bits may be implemented inside the user application. table 13: x-interrupt detailed mapping gives an overview of the different settings available. 2.3.1 hardware impact none. 2.3.2 software impact first, the xmiscen bit, that is, bit 10 of the xpercon register, must be set to have access to these registers. refer to section 3.1: xpercon register for more details. then, the xirxsel registers must be configured. if none of the new xperipherals is used, that is, only the xperipherals that were already present on the st10f269zx are used, the following values must be programmed: xir0sel = 0x0100, only the can1 interrupt is enabled and can generate an interrupt to the st10 through xp0ic xir1sel = 0x0100, only the can2 interrupt is enabled and can generate an interrupt to the st10 through xp1ic xir2sel = 0x0, not used xir3sel = 0x2000, only the pll unlock interrupt is enabled and can generate an interrupt to the st10 through xp3ic table 13. x-interrupt detailed mapping xp0int xp1int xp2int xp3int can1 interrupt x x can2 interrupt x x i2c receive x x x i2c transmit x x x i2c error x ssc1 receive x x x ssc1 transmit x x x ssc1 error x asc1 receive x x x asc1 transmit x x x asc1 transmit buffer x x x asc1 error x pll unlock / owd x pwm1 channel 3...0 x x
AN2549 new features 19/33 then, in the interrupt routines associated with the xpxic, the respective flags in the xirxsel registers must be cleared. since the xirxsel registers are not bit addressable, a pair of registers (a pair for each xirxsel) is provided to set and clear the bits of xirxsel without risking to overwrite requests coming after reading the register and before writing it. therefore, the following registers must be written to clear the flags: in the can1 interrupt routine, xir0clr (@ eb14h) = 0x0001 in the can2 interrupt routine, xir1clr (@ eb24h) = 0x0001 in the pll unlock interrupt routine, xir3clr (@ eb44h) = 0x0020 additional information on the x-interrupt multiplexer structure figure 2: x-interrupt basic structure shows that the x-interrupt sources are connected to the interrupt request flag of the xirxsel registers and to the xpxir request flag via an and gate with the enable bit. this and gate is activated by a transition on the interrupt source line and not by the latched value in the xirxsel register. this means that: a transition on the it source line generates an interrupt to the st10 core if the source is enabled. writing to an interrupt request flag in an xirxsel register does not generate an interrupt to the st10 core. example: if xir0sel = 0x0100: can1 interrupt enabled on xp0ic interrupt to trigger by software the can1 interrupt routine with the xp0ic register, the following code must be used: xir0set = 0x0001;/* set can1 interrupt request flag in xir0sel */ xp0ic = xp0ic | 0x0080;/* set xp0ir flag, generate an interrupt */ executing only the first line only sets the flag in the xir0sel register but it is not seen by the and gate and cannot set the xp0ir flag.
AN2549 new features 20/33 2.4 additional ports input control the possibility to select betw een ttl and cmos-lik e input thresholds has been extended to ports 0, 1 and 5 via the xpicon register. 2.4.1 hardware impact none. 2.4.2 software impact none. st10f272z2: xpicon (eb26h) xreg reset value: --00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved p5 hin p5 lin p1 hin p1 lin p0 hin p0 lin - r/w r/w r/w r/w r/w r/w table 14. xpicon register description bit function reset value pxlin port x low byte input level selection 0: pins px.7..0 switch on standard ttl input levels 1: pins px.7..0 switch on cmos input levels 0 pxhin port x high byte input level selection 0: pins px.15..8 switch on standard ttl input levels 1: pins px.15..8 switch on cmos input levels 0
AN2549 modified registers 21/33 3 modified registers 3.1 xpercon register in the st10f272z2, new bits have been added with regards to the additional xperipherals. the xpercon register allows th e xbus peripherals to be se parately selected and made visible to the user by means of the corresponding bits. if an xbus peripheral is not selected (not activated with a bit of xpercon) before the xpen bit in syscon is set, the corresponding address space, port pins and interrupts are not occupied by the peripheral, and thus this peripheral is not visible and not available. st10f269zx: xpercon (f024h / 12h) sfr reset value: --05h 1514131211109876543210 reserved rtc en xram2 en xram1 en can2 en can1 en - r/w r/w r/w r/w r/w st10f272z2: xpercon (f024h/12h) sfr reset value: -005h 1514131211109876543210 reserved xmisc en xi2c en xssc en xasc en xpwm en res. rtc en xram2 en xram1 en can2 en can1 en - r/w r/w r/w r/w r/w - r/w r/w r/w r/w r/w table 15. xpercon register description bit bit name function 15:11 - reserved 10 xmiscen xbus additional features enable bit 0: accesses to the additional miscellaneous features is disabled. 1: the additional features are enabled and can be accessed. 9xi2cen xi 2 c enable bit 0: accesses to the on-chip xi 2 c are disabled, external access performed. 1: the on-chip xi 2 c is enabled and can be accessed. 8 xsscen xssc enable bit 0: accesses to the on-chip xssc ar e disabled, external access performed. 1: the on-chip xssc is enabled and can be accessed. 7 xascen xasc enable bit 0: accesses to the on-chip xasc ar e disabled, external access performed. 1: the on-chip xasc is enabled and can be accessed. 6xpwmen xpwm enable 0: accesses to the on-chip xpwm mo dule are disabled, external access performed. 1: the on-chip xpwm module is enabled and can be accessed. 5-reserved
AN2549 modified registers 22/33 accesses to the xperipherals are configured through three pairs of specific xbus configuration registers, equivalent to the external bus register busconx and addrselx. therefore, several xperipherals are sharing the same pair, with the consequence that accesses to a disabled xperipherals are only redirected to external memory if all the other xperipherals sharing the same pair of registers are disabled. the xperipherals are grouped as follows: can1, can2, xasc, xssc, xi2c, xpwm, xrtc and xmisc: accesses to the 00?e800h-00?efffh range are redirected to external memory only if all corresponding bits are cleared xram1: accesses to the 00?e000h-00?e7ffh range are redirected to external memory if bit xram1en is cleared xram2: accesses the 09?0000h-0f?ffffh range (default value in xadrs3 register, refer to section 4.1: xadrs3 register ) are redirected to external memory if bit xram2en is cleared 3.1.1 hardware impact none. 3.1.2 software impact none if the st10f269zx software is not writing to the reserved bit. 4rtcen rtc enable bit 0: accesses to the on-chip real time clock are disabled, external access performed. 1: the on-chip real time clock is enabled and can be accessed. 3xram2en xram2 enable bit 0: accesses to the on-chip xram2 block are disabled, external access performed. 1: the on-chip xram2 is enabled and can be accessed. 2xram1en xram1 enable bit 0: accesses to the on-chip xram1 block are disabled, external access performed. 1: the on-chip xram1 is enabled and can be accessed. 1can2en can2 enable bit 0: accesses to the can2 xperipheral and its functions are disabled (p4.4 and p4.7 pins can be used as general purpose i/os) 1: the can2 xperipheral is enabled and can be accessed. 0can1en can1 enable bit 0: accesses to the can1 xperipheral and its functions are disabled (p4.5 and p4.6 pins can be used as general purpose i/os) 1: the can1 xperipheral is enabled and can be accessed. table 15. xpercon register description (continued) bit bit name function
AN2549 new registers 23/33 4 new registers 4.1 xadrs3 register on previous st10 devices, this register was already present but its value was mask programmed. on the st10f272z2 this register has been made available to the user. in this way the address range of the xram2 memory is now user-programmable. the register functionality is the same as that of addrselx registers used for external address range selection, with some limitations: the address window can only be located in the first megabyte of addressable space, that is, in the 00?0000h-0f?ffffh range the window start address must be aligned to a range size boundary 4.1.1 hardware impact none. st10f272z2: xadrs3 (f01ch) sfr reset value: 800bh 1514131211109876543210 rgsad rgsz r/w r/w table 16. xadrs3 register description bit bit name function 15:4 rgsad range start address defines the bits a19..a8 of the start address of the address window. 3:0 rgsz range size selection defines the size of the address window. table 17. definition of address area bit field rgsz selected window size relevant bit (r) of rgsad selected range start address relevant bit (r) of address (a23 - a0) 0 0 0 0 256 bytes rrrr rrrr rrrr 0000 rrrr rrrr rrrr xxxx xxxx 0 0 0 1 512 bytes rrrr rrrr rrrx 0000 rrrr rrrr rrrx xxxx xxxx ... ... ... ... 1 0 1 0 256 kbytes rrxx xxxx xxxx 0000 rrxx xxxx xxxx xxxx xxxx 1 0 1 1 512 kbytes rxxx xxxx xxxx 0000 rxxx xxxx xxxx xxxx xxxx 1 1 x x reserved
AN2549 new registers 24/33 4.1.2 software impact on st10f272z2, this register must be programmed by the user before accessing xram2 so that: rgsz defines a 16 kbyte window size. rgsz = 0110b rgsad defines bits 8 to 19 of the window start address aligned to a 16-kbyte boundary (the least significant bits of the field are not relevant). in the st10f272z2, the xram2 cannot be located within page 3 of segment 0. the user can either: map the xram2 from anywhere above address 09?0000h map the xram2 in the 16-kbyte page available in segment 0 in the 00?8000h - 00?bfffh range. the desired value should be written in xadrs3 register before enabling xram2 in the syscon and xpercon registers. note: xadrs3 cannot be changed after executing the einit instruction. example to map the 16-kbyte xram2 onto page 60 (starting address 0f?0000h, compatible with the st10f276e), then xadrs3 must be initialized with the value f006h. to map the 16-kbyte xram2 onto page 2 (starting address 00?8000h), then xadrs3 must be initialized with the value 0806h. variables and pec transfers for architecture reasons, the pec destination and source pointers must be in the segment 0. therefore, all ram variables and arrays that are pec-addressed must be located in ram memory available in segment 0 (dpram + xram1, and xram2 if remapped onto page 3). about toolchain memory model a change in the toolchain configuration is needed to take into account the xram2?s new location. in the st10f269zx, all the xram is in page 3 and it is then automatically addressed using dpp3 that points to page 3 (in order to access the dpram and the sfr/esfr). for the st10f272z2, it is necessary to dedicate a dpp to access some of xram2. example in case of small memory model with tasking toolchain the small memory model makes it possible to have a total code size up to 16 mbytes, up to 64 kbytes of fast accessible 'normal user data' in three different memory configurations and the possibility to acce ss far/huge data, if more than 64 kbytes of data is needed.
AN2549 new registers 25/33 the three memory configurations possible for this 64 kbytes of 'normal user data' are: default the four dpp registers are assumed to contain their system startup value (0-3), providing one linear data area of 64 kbytes in the first segment (00?0000h - 00?ffffh). addresses linear dpp3 contains page number 3, allowing access to system (extended) sfr registers and bit-addressable memory. dpp0 - dpp2 provide a linear data area of 48 kbytes anywhere in memory. paged dpp3 contains page number 3, allowing access to system (extended) sfr registers and bit-addressable memory. dpp0, dpp1 and dpp2 contain the page number of a data area of 16 kbytes anywhere in memory. therefore, mapping the xram2 onto page 2 (segment 0) makes it available for pec transfer and the default configuration of the c compiler toolchains can still be used. 4.2 xperemu register this register has been added as a write-only register. the bit meaning is exactly the same as in the xpercon register. 4.2.1 hardware impact none. 4.2.2 software impact once the xpen bit of the syscon register is set and at least one of the xperipherals (except for memories) is activated, the xperem u register must be wr itten with the same contents as the xpercon register : this is mandatory in order to allow a correct emulation of the new set of features introduced on xbus for the new st10 generation. the following instructions must be added in side the initialization routine: if (syscon.xpen && (xpercon & 0x07d3)) then {xperemu = xpercon} of course, xperemu must be programmed after xpercon and afte r syscon. in this way, the final configuration for xperipherals is stored in xperemu and used for the emulation hardware setup. st10f272z2: xperemu (eb7eh) xreg reset value: xxxxh 1514131211109876543210 reserved xmis cen xi2 cen xss cen xas cen xpw men res. xrt cen xram2 en xram1 en can2 en can1 en - wowowowowo - wowowowowo
AN2549 new registers 26/33 4.3 emulation-dedicated registers a set of four additional registers is implemented for emulation purposes only. similarly to the xperemu, they are write-only registers. xemu0 (00?eb76h) xemu1 (00?eb78h) xemu2 (00?eb7ah) xemu3 (00?eb7ch) these registers are used by emulators. they have no user action on the st10f272z2. 4.3.1 hardware impact none. 4.3.2 software impact none. on the st10f269zx, the 00?e800h to 00?ebffh address range was mapped to external memory but is recommended to reserve this space for upward compatibility. 4.4 xmisc register this register has been created to handle some ad ditional functionalities. to have access to this register, the xmiscen bit, that is, bit 10 of xpercon, must be set. st10f272z2: xmisc (eb46h) xreg reset value: 0000h 1514131211109876543210 reserved vreg off can ck2 can pa r adc mux - r/w r/w r/w r/w table 18. xmisc register description bit bit name function 15:4 - reserved 3vregoff main voltage regulator disable in power-down mode 0: default value after reset and when power-down is not used 1: on-chip main regulator is turned off when power-down mode is entered 2 canck2 can clock divider by 2 disable 0: clock provided to can modules is cpu clock divided by 2 (mandatory when f cpu is higher than 40 mhz) 1: clock provided to can modules is directly cpu clock
AN2549 new registers 27/33 4.4.1 hardware impact none. 4.4.2 software impact none. 1canpar can parallel mode selection 0: can2 is mapped on p4.4/p4.7, while can1 is mapped on p4.5/p4.6 1: can1 and can2 are mapped in parallel on p4.5/p4.6. this is effective only if both can1 and can2 are enabled (bits can1en and can2en set in xpercon register). if can1 is disabled, can2 remains on p4.4/p4.7 even if the canpar bit is set. 0 adcmux port1l adc channels enable 0: analog inputs on port p5.y can be converted (default configuration) 1: analog inputs on port p1.z can be converted. only 8 channels can be managed table 18. xmisc register description (continued) bit bit name function
AN2549 electrical characteristics 28/33 5 electrical characteristics note: in the tables where the device provides signa ls with their respective timing characteristics, the symbol cc (controller characteristics) is included in the symbol column. in the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol sr (system requirement) is included in the symbol column. 5.1 dc characteristics 5.1.1 absolute maximum ratings they are the same. 5.1.2 overview of the dc characteristics the pads of the st10f272z2 have been redesigned according to the new technology and therefore the characteristics are different. the user should verify the dc characteristics. ta bl e 1 9 lists the parameters that might be impacted most. table 19. dc characteristics symbol parameter st10f269zx limit values st10f272z2 limit values unit min max min max v il sr input low voltage (all inputs) -0.5 0.2 v dd - 0.1 -0.3 0.8 v v ils sr -0.5 2.0, special threshold -0.3 0.3 v dd , special threshold v il1 sr input low voltage (rstin , ea, nmi, and rpd) n.a. n.a. -0.3 0.3 v dd v v il2 sr input low voltage (xtal1 and xtal3) -0.3 0.3 v dd v v ih sr input high voltage (all except rpd, xtal1 and xtal3) 0.2 v dd + 0.9 v dd + 0.5 2.0 v dd + 0.3 v v ihs sr 0.8 v dd - 0.2 v dd + 0.5, special threshold 0.7 v dd v dd + 0.3, special threshold hys cc input hysteresis n.a. 400, special threshold - 400, default 750, special threshold 700 1400 mv v hys1 cc input hysteresis rstin , ea , nmi 750 1400 mv
AN2549 electrical characteristics 29/33 5.2 ac characteristics at 40 mhz as the two devices have a different technology, the i/os also present some differences in the ac behavior. the tables below ( ta b l e 2 0 and ta b l e 2 1 ) list all the timing differences. please check carefully your desig n for possible impact. 5.2.1 external memory bus timings note that for cpu clock frequencies above 40 mhz (for st10f272z2q3 devices), some numbers in the timing formulas become zero or negative, that in most of the cases is not acceptable or not meaningful at all. in these cases, it is necessary to reduce the speed of the bus setting properly t a (ale extension), t c (memory cycle time wait-states) and t f (memory tri-state time). v ol cc output low voltage ? port0, port1, port4, ale, rd , wr , bhe , clkout, rstout 0.45 / i ol = 2.4ma ? port6, ale, clkout, wr , ready, bhe , rd , rstout , rstin 0.4 / i ol = 8ma 0.05 / i ol = 1ma v v ol1 cc output low voltage (all other) ?0.45/i ol = 2.4ma ?0.4/i ol =4ma 0.05 / i ol =0.5ma v v oh cc output high voltage 0.9v dd /i oh = -0.5ma 2.4 / i oh = -2.4ma ? port0, port1, port4, rd , ale, bhe , wr, clkout, rstout v dd - 0.8 / i oh = -8ma v dd - 0.08/ i oh = -1ma ? port6, ale, clkout, wr , ready, bhe , rd , rstout , rstin v v oh1 cc output high voltage (all other) 0.9v dd /i oh = -0.25ma 2.4 / i oh = -1.6ma ? v dd - 0.8 / i oh = -4ma v dd -0.08/i oh = -0.5ma ?v i oz1 cc input leakage current (port 5) ? 0.5 ? 0.2 a i oz2 cc input leakage current (all other inputs) ?1?0.5a table 19. dc characteristics (continued) symbol parameter st10f269zx limit values st10f272z2 limit values unit min max min max
AN2549 electrical characteristics 30/33 multiplexed bus demultiplexed bus table 20. multiplexed bus timings (ns) symbol parameter st10f269zx st10f272z2 st10f269zx @f cpu = 40 mhz st10f272z2 @f cpu = 40 mhz min max min max min max min max t 6 cc address setup to ale tcl - 10.5 + t a - tcl - 11 + t a -2 + t a - 1.5 + t a - t 16 sr ale low to valid data in - 3 tcl - 19 + t a + t c - 3 tcl - 20 + t a + t c 18.5 + t a + t c - 17.5 + t a + t c - t 17 sr address/unlatch ed cs to valid data in - 4 tcl - 28 + 2t a + t c - 4 tcl - 30 + 2t a + t c 22 + 2t a + t c - 20 + 2t a + t c - t 39 sr latched cs low to valid data in - 3 tcl - 19 + 2t a + t c - 3 tcl - 21 + 2t a + t c 18.5 + 2t a + t c - 16.5 + 2t a + t c - t 44 cc address float after rdcs , wrcs (with rw delay) -0-1.5-0-1.5 t 45 cc address float after rdcs , wrcs (no rw delay) - tcl - tcl + 1.5 - 12.5 - 14 table 21. demultiplexed bus timings symbol parameter st10f269zx st10f272z2 st10f269zx @f cpu = 40 mhz st10f272z2 @f cpu = 40 mhz min max min max min max min max t 6 cc address setup to ale tcl - 10.5 + t a - tcl - 11 + t a -2 + t a - 1.5 + t a - t 80 cc address/unlatched cs setup to rd , wr (with rw delay) - 2 tcl - 8.5 + 2t a - 2 tcl - 12.5 + 2t a 16.5 + 2t a - 12.5 + 2t a - t 81 cc address/unlatched cs setup to rd , wr (no rw delay) - tcl - 8.5 + 2t a - tcl - 12 + 2t a 4 + 2t a - 0.5 + 2t a - t 16 sr ale low to valid data in - 3 tcl - 19 + t a + t c - 3 tcl - 20 + t a + t c 18.5 + t a + t c - 17.5 + t a + t c - t 17 sr address/unlatched cs to valid data in - 4 tcl - 28 + 2t a + t c - 4 tcl - 30 + 2t a + t c 22 + 2t a + t c - 20 + 2t a + t c -
AN2549 electrical characteristics 31/33 5.2.2 hi-speed synchronous serial in terface (ssc) the maximum baudrate of the ssc in the st10f272z2 is 8 mbaud whereas it is 10 mbaud in the st10f269zx. for cpu frequencies strictly higher than 32 mhz, the minimum value in the sscbr register (prescaler value) must not be lower than 2. t 28 cc address/unlatched cs hold after rd , wr 0 (no t f ) -5 + t f (t f > 0) -0 + t f - 0 (no t f ) -5 + t f (t f > 0) -0 + t f - t 39 sr latched cs low to valid data in - 3 tcl - 19 + 2t a + t c - 3 tcl - 21 + 2t a + t c 18.5 + 2t a + t c - 16.5 + 2t a + t c - t 82 cc address setup to rdcs , wrcs (with rw delay) 2 tcl - 10.5 + 2t a - 2 tcl - 11 + 2t a - 14.5 + 2t a - 14 + 2t a - table 21. demultiplexed bus timings (continued) symbol parameter st10f269zx st10f272z2 st10f269zx @f cpu = 40 mhz st10f272z2 @f cpu = 40 mhz min max min max min max min max
AN2549 revision history 32/33 6 revision history table 22. revision history date revision changes 05-july-2007 1 initial release
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